Metallic silicides have been used as an interconnection material in integrated circuits in order to overcome certain inherent disadvantages of polycrystalline silicon. The primary disadvantage of such is its minimum sheet resistivity that is about 10 ohms/square. Various metallic suicides have been used on the polycrystalline silicon because of the reduced sheet resistance, in order to improve the performance of large scale integrated circuits. The metallic silicides permit the scaling down of interconnect and gate line widths that is required to achieve very large scale integration. However, the conventional method of forming suicides on the surfaces of a polycrystalline silicon gate referred to as "Salicide" processing does not result in a self-aligned insulator on the gate conductor Accordingly, such is not readily suitable for borderless contacts that are used in high density ULSI. On the other, polycide gate conductors, while incorporating the insulating cap for borderless contacts, are extremely difficult to fabricate. In particular, the conductor is put in place early in the fabrication sequence and therefore, must withstand oxidation, wet chemical cleaning and high thermal cycles.
Reference to FIG. 1 illustrate the typical starting stack in the prior art for the polycide gate process. In particular, after gate oxidation and poly deposition, a refractory metal or metal silicide (such as W, WSI.sub.2 or TiSi.sub.2) is deposited and capped with a dielectric such as silicon nitride (Si.sub.3 N.sub.4). A diffusion barrier is sometimes employed between the gate conductor and the polysilicon to prevent interaction and transport of dopants.
The gate is then defined by photolithography and reactive ion etching and a dielectric sidewall is then formed by chemical vapor deposition followed by reactive ion etching. The resulting structure in the prior art is illustrated in FIG. 2.
FIG. 3 illustrates the contact of the substrate material with overlap to gate permitted (for increased density) with such a gate structure. The capping material and field dielectrics are selected such that the contact etch will not etch through the gate cap when sufficient etching is done to contact the substrate.
The problems encountered when fabricating such structures are numerous. First of all, the multiple layer structure as illustrated in FIG. 1 is extremely difficult to reactive ion etch without undercutting and/or line with bias due to the dissimilar materials present. In addition, after the reactive ion etching of the gate, a sidewall oxidation step is typically required, both to act as a pad oxide for a subsequent nitride sidewall, and to repair gate oxide damage. Metals such as tungsten and diffusion barriers such as titanium nitride or tantalum nitride oxidize very readily. Furthermore, wet cleans such as sulphuric acid-peroxide compositions or HuangB, acid-peroxide compositions, water-peroxide-hydrochloric acid or water-peroxide-amonium hydroxide compositions, are often used after gate reactive ion etching, in order to remove residue from the reactive ion etching. However, many of the conductors employed are etched by such solutions.
Another disadvantage is that the patterned gate must withstand the thermal cycles that are used to drive and activate the dopants for the source/drain junctions. Even for very shallow functions, these thermal cycles can be significant (e.g., about 900.degree. C. for about 5 minutes or about 100.degree. C. for about 5 seconds). Materials such as titanium silicide or cobalt silicide are not stable on polycrystalline silicon for these thermal cycles and therefore, require a diffusion barrier. However, the common diffusion barrier materials such as TiW, TiN and TiB are easily oxidized and readily attacked by the wet etchants. On the other hand, materials such as tungsten are chemically resistant but oxidize much too easily. Materials such as WSi.sub.2 are more stable, but exhibit higher resistivity and therefore are not an option for deep submicron lines where sheet resistances of less than 10 ohm/square are required. Finally, in these situations, the polysilicide conductor line width is limited to be less than or equal to the gate length. Therefore, as device dimensions are scaled down, extremely high aspect ratios cannot be avoided if resistance targets remain relatively constant.